The present invention relates generally to semiconductor device processing techniques, and, more particularly, to a structure and method for forming asymmetrical overlap capacitance in field effect transistors (FETs).
In the manufacture of semiconductor devices, there is a constant drive to increase the operating speed of certain integrated circuit devices such as microprocessors, memory devices, and the like. This drive is fueled by consumer demand for computers and other electronic devices that operate at increasingly greater speeds. As a result of the demand for increased speed, there has been a continual reduction in the size of semiconductor devices, such as transistors. For example, in a device such as a field effect transistor (FET), device parameters such as channel length, junction depth and gate dielectric thickness, to name a few, all continue to be scaled downward.
Generally speaking, the smaller the channel length of the FET, the faster the transistor will operate. Moreover, by reducing the size and/or scale of the components of a typical transistor, there is also an increase in the density and number of the transistors that may be produced on a given amount of wafer real estate, thus lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
Unfortunately, reducing the channel length of a transistor also increases “short channel” effects, as well as “edge effects” that are relatively unimportant in long channel transistors. One example of a short channel effect includes, among other aspects, an increased drain to source leakage current when the transistor is supposed to be in the “off” or non-conductive state, due to an enlarged depletion region relative to the shorter channel length. In addition, one of the edge effects that may also adversely influence transistor performance is what is known as Miller capacitance. The Miller capacitance is a parasitic overlap capacitance (Cov) that arises as a result of the doped polycrystalline silicon gate electrode and gate dielectric that (almost invariably) overlaps with a conductive portion of the more heavily doped source/drain regions and/or the less heavily doped source/drain extension (SDE) regions (if present) of the FET.
Moreover, as transistor dimensions continue to scale down, the gate to source/drain extension overlap needs to be kept relatively constant so that drive current can be maintained. For example, a minimum of about 20 nm/side of overlap is necessary to prevent transistor drive current (Idsat) degradation. When an overlap is too small, a high resistance region will be created between the extension and the channel. As devices become smaller, the source extension to drain extension distance becomes narrower, resulting in a severe punch through problem.
Accordingly, it would be desirable to be able to fabricate an FET device that maintains a low series resistance between the gate and the source of the device, while at the same time minimizing adverse consequences such as short channel effects, hot carrier effects, punch through and parasitic Miller capacitance formed by excessive gate to drain overlap.